El acta ha sido enviada 28 Jan 201228/01/12 at 17:342012-01-28 17:34:28

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Tarea 3 (Fecha entrega: 17/01/2012) 5 Jan 201205/01/12 at 12:012012-01-05 12:01:05

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Tarea 3 5 Jan 201205/01/12 at 11:592012-01-05 11:59:05

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Tarea 2 5 Jan 201205/01/12 at 11:532012-01-05 11:53:05

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Encuesta Docente de Mitad de Semestre 5 Dec 201105/12/11 at 10:022011-12-05 10:02:05

Tarea 1 27 Nov 201127/11/11 at 23:352011-11-27 23:35:27

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Tarea 2 (Fecha entrega: 11/12/2011) 27 Nov 201127/11/11 at 23:152011-11-27 23:15:27

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Tarea2 27 Nov 201127/11/11 at 23:142011-11-27 23:14:27

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dc_setting 21 Nov 201121/11/11 at 15:352011-11-21 15:35:21

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Clases mañana miercoles 9 8 Nov 201108/11/11 at 11:292011-11-08 11:29:08

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Tarea 1 (Fecha entrega: 16/11/2011) 2 Nov 201102/11/11 at 17:402011-11-02 17:40:02

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El servicio 'Tareas' ha sido activado 2 Nov 201102/11/11 at 17:392011-11-02 17:39:02

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Tarea1 2 Nov 201102/11/11 at 17:362011-11-02 17:36:02

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synopsys_dc.setup 2 Nov 201102/11/11 at 17:102011-11-02 17:10:02

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High Level Simulation 2 Nov 201102/11/11 at 17:032011-11-02 17:03:02

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Conectarse al Servidor 2 Nov 201102/11/11 at 17:012011-11-02 17:01:02

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0. Introduccion 25 Oct 201125/10/11 at 11:562011-10-25 11:56:25

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11. Design for Test 25 Oct 201125/10/11 at 11:552011-10-25 11:55:25

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10. Low Power Design 25 Oct 201125/10/11 at 11:542011-10-25 11:54:25

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9. Test Benches and Verification 25 Oct 201125/10/11 at 11:542011-10-25 11:54:25

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8. Finite state machines 25 Oct 201125/10/11 at 11:532011-10-25 11:53:25

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6. Design with verilog 25 Oct 201125/10/11 at 11:532011-10-25 11:53:25

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7. Hierarchy and partitioning 25 Oct 201125/10/11 at 11:532011-10-25 11:53:25

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5. How to design complex digital systems 25 Oct 201125/10/11 at 11:522011-10-25 11:52:25

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4. Introduction to Design with Verilog 25 Oct 201125/10/11 at 11:522011-10-25 11:52:25

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