Control N° 1 13 Oct 202413/10/24 at 19:432024-10-13 19:43:13

Francisco Rivera

Clase de Mañana Viernes 04/10 3 Oct 202403/10/24 at 19:342024-10-03 19:34:03

Francisco Rivera

Encuesta Docente de Mitad de Semestre (2023) 1 Oct 202401/10/24 at 12:022024-10-01 12:02:01

Tarea N° 2 (Fecha entrega: 15/10/2024) 29 Sep 202429/09/24 at 19:122024-09-29 19:12:29

Francisco Rivera

Diseño Verilog Vending Machine 26 Sep 202426/09/24 at 19:342024-09-26 19:34:26

Francisco Rivera

Diseño Vending Machine Parte II 12 Sep 202412/09/24 at 21:062024-09-12 21:06:12

Francisco Rivera

Diseño Vending Machine Parte I 12 Sep 202412/09/24 at 21:022024-09-12 21:02:12

Francisco Rivera

Tarea N° 1 (Fecha entrega: 01/10/2024) 10 Sep 202410/09/24 at 20:262024-09-10 20:26:10

Francisco Rivera

Control N° 1 8 Sep 202408/09/24 at 21:562024-09-08 21:56:08

Francisco Rivera

Control N° 2 8 Sep 202408/09/24 at 21:562024-09-08 21:56:08

Francisco Rivera

Controladores Multi-Entradas 6 Sep 202406/09/24 at 20:082024-09-06 20:08:06

Francisco Rivera

Sistemas Secuenciales y Verilog / SystemVerilog 4 Sep 202404/09/24 at 21:272024-09-04 21:27:04

Francisco Rivera

Sistemas Combinacionales y Verilog / SystemVerilog 4 Sep 202404/09/24 at 21:252024-09-04 21:25:04

Francisco Rivera

HDL Verilog / SystemVerilog 23 Aug 202423/08/24 at 18:502024-08-23 18:50:23

Francisco Rivera

IEEE_Std 1800-2023 SystemVerilog 22 Aug 202422/08/24 at 20:242024-08-22 20:24:22

Francisco Rivera

Mnemónicos Polarizados y Tecnología 22 Aug 202422/08/24 at 20:232024-08-22 20:23:22

Francisco Rivera

Minimización Expresiones Booleanas: Mapa MEV 8 Aug 202408/08/24 at 22:162024-08-08 22:16:08

Francisco Rivera

Descripción y Evaluación del Curso 8 Aug 202408/08/24 at 22:142024-08-08 22:14:08

Francisco Rivera