Plazo tarea 4 27 Oct 201327/10/13 at 23:242013-10-27 23:24:27

Ignacio Barrueto Gonzalez

Re: Paralelismo 26 Oct 201326/10/13 at 20:282013-10-26 20:28:26

Rene Espinoza Jimenez

Paralelismo 26 Oct 201326/10/13 at 17:382013-10-26 17:38:26

Felipe Besser P.

Re: Duda tarea 3 22 Oct 201322/10/13 at 00:452013-10-22 00:45:22

Rene Espinoza Jimenez

Re: Duda tarea 3 21 Oct 201321/10/13 at 23:522013-10-21 23:52:21

Alex J. Díaz Millan

Re: Duda tarea 3 21 Oct 201321/10/13 at 20:332013-10-21 20:33:21

Rene Espinoza Jimenez

Duda tarea 3 21 Oct 201321/10/13 at 20:262013-10-21 20:26:21

Matias Vidal Valladares

Tarea1 20 Oct 201320/10/13 at 21:012013-10-20 21:01:20

Rene Espinoza Jimenez

Auxiliar 3 20 Oct 201320/10/13 at 19:592013-10-20 19:59:20

Rene Espinoza Jimenez

Auxiliar3.avi 20 Oct 201320/10/13 at 19:562013-10-20 19:56:20

Rene Espinoza Jimenez

ejemplo_testbench.rar 20 Oct 201320/10/13 at 19:472013-10-20 19:47:20

Rene Espinoza Jimenez

Diseño FPGA Vending Machine 14 Oct 201314/10/13 at 13:452013-10-14 13:45:14

Francisco Rivera

Encuesta Docente de Mitad de Semestre 10 Oct 201310/10/13 at 11:202013-10-10 11:20:10

Encuesta Docente de Mitad de Semestre 10 Oct 201310/10/13 at 11:202013-10-10 11:20:10

Control #1 9 Oct 201309/10/13 at 13:332013-10-09 13:33:09

Francisco Rivera

Re: RECLAMO Ejercicio #1 9 Oct 201309/10/13 at 02:102013-10-09 02:10:09

José Ogalde

Re: RECLAMO Ejercicio #1 9 Oct 201309/10/13 at 01:332013-10-09 01:33:09

Alex J. Díaz Millan

Respecto a las Tareas 8 Oct 201308/10/13 at 19:272013-10-08 19:27:08

Rene Espinoza Jimenez

Re: RECLAMO Ejercicio #1 8 Oct 201308/10/13 at 19:072013-10-08 19:07:08

Rene Espinoza Jimenez

RECLAMO Ejercicio #1 7 Oct 201307/10/13 at 23:182013-10-07 23:18:07

Daniel Jiménez B.

Re: Error Enunciado tarea 2 7 Oct 201307/10/13 at 22:562013-10-07 22:56:07

José Ogalde

Re: Error Enunciado tarea 2 7 Oct 201307/10/13 at 22:492013-10-07 22:49:07

Daniel Jiménez B.

Re: Error Enunciado tarea 2 7 Oct 201307/10/13 at 22:132013-10-07 22:13:07

José Ogalde

Re: Error Enunciado tarea 2 7 Oct 201307/10/13 at 20:252013-10-07 20:25:07

Matias Vidal Valladares

Diseño CPLD & FPGA 7 Oct 201307/10/13 at 19:542013-10-07 19:54:07

Francisco Rivera